1. Field of the Invention
The present invention relates to optical information reproduction apparatuses for reproducing digital information recorded in an optical information recording medium, and more particularly, to an optical information reproduction apparatus for reproducing digital information by sampling a binary-converted reproduction signal with a clock signal.
2. Description of the Related Art
There are known many optical information recording media in which information is recorded with an optical beam or from which recorded information is read with an optical beam. Some of them can be recorded and reproduced, and some are reproduced only. They have various shapes, such as those of disks, cards, and tape. Among these optical information recording media, it is considered that applications for optical cards will extend due to their features of easy production, superior portability, and accessibility. Various optical information recording and reproducing apparatuses have been proposed for optical cards.
In such an optical information recording and reproducing apparatus, recording and reproduction are performed with continuous control of automatic tracking and automatic focusing. To record information on a recording medium in the apparatus, an optical beam converged to a minute spot is modulated according to the information to be recorded and an information track is scanned with the modulated optical beam. With the beam irradiation as described above, a piece of information is recorded on an information track as an information pit row which can be detected optically. To reproduce information recorded on a recording medium, an information pit row on an information track is scanned with an optical beam having a constant power which does not cause recording on the medium, and the light reflected from or passing through the medium is detected.
FIG. 1 is a block diagram illustrating an outlined configuration of a typical optical information recording and reproducing apparatus which employs the information recording and reproducing method described above.
In FIG. 1, the optical information recording and reproducing apparatus comprises a semiconductor laser 101; a collimator lens 102, a diffraction grating 103, a polarized-beam splitter 104, a quarter-wavelength plate 105, and an objective lens 106 placed in that order in the direction in which the light flux emitted from the semiconductor laser 101 advances; and a toric lens 108 and an optical detector 109 placed in that order in the direction in which the light flux separated by the polarized-beam splitter 104 advances. An optical card 107 is placed at the focus of the objective lens 106.
In the above-described optical information recording and reproducing apparatus, the light flux (S polarized light) emitted from the semiconductor laser 101 is made parallel by the collimator lens 102, and then divided into a plurality of light flux by the diffraction grating 103. The divided light flux is converged on the optical card 107 through the polarized-beam splitter 104, the quarter-wavelength plate 105, and the objective lens 106.
The light reflected from the optical card 107 passes through the objective lens 106 and the quarter-wavelength plate 105, and is made to P polarized light. The light is reflected by the polarized-beam splitter 104, and enters the optical detector 109 through the toric lens 108.
Among light flux divided by the diffraction grating 103, the 0th-order diffraction light ray is used to record and reproduce information and to perform automatic focusing control (hereinafter called AF). Automatic tracking control (hereinafter called AT) is performed with the positive and negative first-order diffraction light rays. The astigmatism method is employed for AF and the three-beam method is used for AT.
FIG. 2A and FIG. 2B illustrate a recording surface of an optical card and the relationship between the recording surface and the scanning speed of an optical spot scanning on the optical card. FIG. 2A is an outlined plan of the optical card. FIG. 2B shows a condition that the scanning speed is not constant at both edges of the optical card.
As shown in FIG. 2A, many information recording and reproducing tracks are arranged in parallel on the optical card 107. Part of the tracks, T1, T2, and T3, are illustrated on the figure. These tracks T1, T2, and T3 are partitioned by tracking tracks tt1 to tt4. The tracking tracks tt1 to tt4 are grooves, or formed with a material having a different reflectance from that of the tracks T1 to T3. The tracking tracks are used as guides for getting a tracking signal.
FIG. 2A shows an example in which information is recorded in or reproduced from the track T3. The 0th-order light ray 110 for recording, reproduction, and AF is emitted to the track T3, and the positive and negative first-order light rays 111 and 112 are emitted to the tracking track tt3 and tt4, respectively. From the reflection light of the positive and negative first-order light rays 111 and 112, a tracking signal, described later, is obtained in order to control the 0th-order diffraction light ray 110 such that it scans exactly on the track T3. The diffraction light rays 110, 111, and 112 scan on the optical card 107 right and left on the figure with a not-shown mechanism with the same positional relationship being maintained.
There are two scanning methods, in which an optical system or an optical card is moved. In either method, since the optical system and optical card reciprocate each other, the scanning speed is not constant at both edges of the optical card. FIG. 2B shows this condition. The horizontal axis shown in FIG. 2B indicates the right and left direction of the optical card and the vertical axis indicates the scanning speed. Usually, the constant-speed scan area, located at the center of the optical card 107, is used for a record area.
The format of an information recording and reproducing track of the optical card 107 will be described next.
FIG. 3A is an example illustrating the format of an information recording and reproducing track of an optical card. On an information recording and reproducing track TN, n data blocks (sectors) are recorded or pre-formatted. FIG. 3B is a view illustrating an example of the format of a data block shown in FIG. 3A.
In FIG. 3A and FIG. 3B, a forward phase-locked-loop synchronizing signal 200 is a continuous repeated data pattern recorded at the top of a data block. By synchronizing this forward PLL synchronizing signal 200 with a sampling clock generated by the PLL control signal generator, data preceded by the forward PLL synchronizing signal 200 is surely reproduced.
A data-read-start-position synchronizing signal 201 recorded between the forward PLL synchronizing signal 200 and a data section D1 indicates the position where data-section read starts. This data-read-start-position synchronizing signal 201 uses a special pattern which is not used in data sections. The data-read-start-position synchronizing signal 201 is recognized as a data-read-end-position synchronizing signal when data is reproduced backward. In data sections D1 to Dm, user data, an error correcting code (ECC), which is a redundant word for detecting and correcting errors, and other items are recorded.
An inter-data synchronizing signal 202 prevents data errors from spreading substantially if the sampling clock is out of synchronization due to dust or scratches in data sections. A special code pattern similar to that used for the data-read-start-position synchronizing signal 201 is used for the inter-data synchronizing signal 202.
A data-read-end-position synchronizing signal 203 is recorded immediately after the last data section in one data block. A special code pattern similar to that used for the data-read-start-position synchronizing signal 201 is used for the data-read-end-position synchronizing signal 203. This data-read-end-position synchronizing signal 203 is recognized as the data-read-start-position signal when the optical beam scans backward.
A backward PLL synchronizing signal 204 is a continuous repeated-data pattern used for synchronizing with a sampling clock generated by the PLL control signal generator, described later, when information is reproduced backward.
Reproduction of information on an information recording and reproducing track of the optical card 107 configured as described above will be described next.
FIG. 4 is an enlarged view of the track to which the diffraction light rays 110, 111, and 112 are emitted as shown in FIG. 2A.
In FIG. 4, the 0th-order diffraction light ray 110 for recording, reproduction, and AF is located at the center between the positive and negative first-order diffraction light rays 111 and 112 for AT, and moves along the center line of the track T3. Hatched sections 113a, 113b, and 113c indicate positions where data is recorded with the 0th-order diffraction light ray 110, which are called pits. Since the pits 113a, 113b, and 113c have a different reflectance from that of the surrounding section, when a weak light scans along the center of the track T3, the reflected light is modulated with the pits 113a, 113b, and 113c, and the reproduction signal is obtained.
FIG. 5 is a circuit diagram illustrating the detail of the optical detector 109 shown in FIG. 1 and a signal processing circuit.
In FIG. 5, the optical detector 109 comprises six optical sensors, an optical sensor 115, an optical sensor 116, and a four-divided optical sensor 114 including four optical sensors. The signal processing circuit comprises a differential circuit 119 which receives the outputs of the optical sensors 115 and 116 and outputs a tracking control signal (At); adding circuits 117 and 118 which receive the outputs of the optical sensors diagonally placed in the four-divided sensor 114, respectively; a differential circuit 120 which receives the outputs of the adding circuits 117 and 118 and outputs a focusing control signal (Af); and a adding circuit 121 which receives the outputs of the adding circuits 117 and 118 and outputs an information reproduction signal (RF).
Optical spots 110a, 111a, and 112a indicate that the reflection light rays of the diffraction light rays 110, 111, and 112 enter the corresponding sensors at those points. The optical spot 110a is located nearly at the center of the four-divided sensor 114. The optical spots 111a and 112a are on the optical sensors 115 and 116.
The outputs of the sensors located diagonally in the four-divided sensor 114 are added in the adding circuits 117 and 118, respectively. The outputs of the adding circuits 117 and 118 are added in the adding circuit 121, and an information reproduction signal RF is reproduced. This means that the information reproduction signal RF corresponds to the entire optical spot 110a located on the four-divided sensor 114.
The outputs of the adding circuits 117 and 118 are also input to the differential circuit 120, and this differential circuit 120 finds the difference of them to form the focusing control signal Af. That is, the focusing control signal Af is the difference between the sums of the outputs of the sensors diagonally arranged in the four-divided optical sensor 114. Since the astigmatism method is precisely described in books, its description is omitted here.
The difference between the outputs of the optical sensors 115 and 116 is obtained in the differential circuit 119 to form the tracking control signal At. Control is usually performed such that At becomes zero, thereby performing tracking control for scanning along the information track with light. The information reproduction signal RF obtained in this way is converted to the binary signal for recognizing it as digital information, then this binary signal is sampled with a sampling clock synchronized with the binary signal to generate the data signal.
FIG. 6 is a block diagram illustrating an example of a processing section which converts the information reproduction signal RF to the binary signal and synchronizes the binary signal RF with the clock signal.
The processing section shown in FIG. 6 comprises a comparator 122 which receives the information reproduction signal RF output from the adding circuit 121 shown in FIG. 5 and a reference voltage ref1, and outputs a binary reproduction signal RF2; a PLL control signal generator connected in parallel to the output line of the comparator 122; and a D flip-flop 123 which receives the output of the comparator 122 and a sampling clock SC generated by the PLL control signal generator and outputs the data signal by sampling the binary reproduction signal RF2 with the sampling clock SC.
The information reproduction signal RF output from the adding circuit 121 shown in FIG. 5 is input to the inverting input terminal of the comparator 122 shown in FIG. 6, and compared with the reference voltage ref1 input to the other input terminal of the comparator 122 to form the binary reproduction signal RF2. The binary reproduction signal RF2 generated by this comparator 122 is input to the D flip-flop 123 and the input terminal R of a phase comparator 124.
The reproduction signal RF2 generated by the comparator 122 is input to the D terminal of the D flip-flop 123 and, in order to cope with fluctuation in the scanning speed of the optical spot, is sampled with the sampling clock SC which is almost synchronized with the binary reproduction signal RF2 and is generated in the PLL control signal generator comprising components 124 to 127, described later, to generate the data signal synchronized with the sampling clock SC.
The data signal generated by the flip-flop 123 is generally controlled by the sampling clock SC and stored in buffer memory. Then, the signal is demodulated by a demodulation circuit not shown in the figure and recognized as digital information (reproduction data).
When the binary reproduction signal RF2 generated by the comparator 122 is input to the input terminal R of the phase comparator 124, the sampling clock SC is almost synchronized with the binary reproduction signal RF2 by the phase comparator 124 in conjunction with a charge pump/loop filter 125, a voltage-controlled oscillator (VCO) 126, and a divider 127. The operations of the phase comparator 124, the charge pump/loop filter 125, the voltage-controlled oscillator (VCO) 126, and the divider 127 will be described below in detail.
FIG. 7 is a circuit diagram illustrating the detailed circuit configuration of the phase comparator 124.
The phase comparator 124 comprises a flip-flop 128, a flip-flop 129, and an AND circuit 130. The clock terminal of the flip-flop 128 is connected to the output line of the comparator 122. The non-inverting output Q of the flip-flop 128 is connected to the data terminal of the flip-flop 129. The inverting output terminal Q' of the flip-flop 129 is connected to the reset terminal R of the flip-flop 128. The clock terminal of the flip-flop 129 is connected to the output line (feedback line for the sampling clock SC) of the divider 127 shown in FIG. 6. The AND circuit 130 receives the feedback signal of the sampling clock SC and the signal output from the non-inverting output terminal Q of the flip-flop 129, and outputs a pulse having a half period of the sampling clock SC.
In the phase comparator 124, the binary reproduction signal RF2 output from the comparator 122 is input to the clock terminal of the D flip-flop 128, and the outputs Q and Q' (Q' is the inverted output of Q) are set high and low, respectively. The non-inverting output Q of the flip-flop 128 is input to the input terminal D of the flip-flop 129, and the sampling clock SC is input to the clock terminal CK of the flip-flop 129. The non-inverting output Q of the flip-flop 128 becomes high, setting the outputs Q and Q' of the flip-flop 129 to high and low, respectively.
The inverting output Q' of the flip-flop 129 is connected to the reset terminal of the flip-flop 128 to reset the flip-flop 128. When the flip-flop 128 is reset, the output Q of the flip-flop 128 becomes low, and the outputs Q and Q' of the flip-flop 129 are inverted to low and high, respectively, at the next sampling clock SC.
As described above, in the phase comparator 124, the flip-flop 128 outputs a phase difference (time difference) pulse from the rising edge of the binary reproduction signal RF2 to the rising edge of the sampling clock SC, and the flip-flop 129 outputs a pulse as wide as one period of the sampling clock SC after the binary reproduction signal RF2 goes high. The pulse of one period and the sampling clock SC are gated by the AND gate 130, outputting the pulse D having a half period.
The details will be described later. When the phase of the binary reproduction signal RF2 matches that of the sampling clock SC, the output pulse of the flip-flop 128 has a width half that of the sampling clock SC. When the phase of the sampling clock SC lags against that of the binary reproduction signal RF2, the width of the pulse becomes larger than half of the period of the sampling clock SC, and when the phase of the sampling clock leads, the width of the pulse becomes smaller than half of the period of the sampling clock SC.
Therefore, in the processing section shown in FIG. 6, the output U or U' (U' is the inverted output of U) of the flip-flop 128, which is a phase-lag signal, is used to increase the frequency of the sampling clock SC, and the output D of the AND circuit 130, which is a phase-lead signal, is used to reduce the frequency of the sampling clock SC.
In other words, the phase difference of the sampling clock SC against the binary reproduction signal RF2 is indicated by the pulse width of the output U or U' of the flip-flop 128 in the above-described processing section. To detect a phase lag or phase lead, the output D of the AND circuit 130, which is a pulse having the half width of the sampling clock SC, is referenced.
To reproduce information from a medium in which the information is recorded using the length of a pit or the length of the gap between pits as in the above-described example, the period of the sampling clock SC is, off course, set so that it corresponds to the minimum pit length (hereinafter called 1T) or equivalent. If a track to be reproduced includes a pit or a gap between pits which is longer than 1T, the rising edge of the sampling clock SC does not match the rising (or falling) edge of the binary reproduction signal RF2 at that pit or gap. Because of this, the phases cannot be compared at each sampling clock SC.
To solve this problem, in the example shown in FIG. 7, phase comparison with the sampling clock SC is performed only at the rising edge of the binary reproduction signal RF2, not at each sampling clock SC. An SR flip-flop which is set by the binary reproduction signal RF2 and reset by the sampling clock SC is required to implement this comparison. In the above-described processing circuit, the operation of an SR flip-flop is achieved by feeding back the inverting output Q' of the D flip-flop 129 to the reset terminal of the flip-flop 128 as shown in FIG. 7.
The operation of the charge pump/loop filter 125 at the timing when the two outputs U' and D of the phase comparator 124 are input to the charge pump/loop filter 125 will be described below in detail.
FIG. 8 is a detailed circuit diagram of the most typical charge pump/loop filter used as the charge pump/loop filter 125.
In FIG. 8, the charge pump/loop filter 125 comprises an amplifier 131, diodes, resistors, and a capacitor. The amplifier 131 receives at the inverting input terminal the output U' of the phase comparator 124 with a backward diode D1 and a resistor R1 inserted in series, connected in parallel with the output D of the phase comparator 124 with a forward diode D2 and a resistor R2 inserted in series. The amplifier 131 also receives the reference voltage ref2 at the other input terminal, and outputs a frequency control signal FC, which is fed back to the inverting input terminal of the amplifier 131 with a resistor R3 and a capacitor C1 being inserted in series to the feedback line.
In the charge pump/loop filter 125, the reference input to the amplifier 131 is the reference voltage ref2. When the two outputs U' and D of the phase comparator 124 are both lower than the reference voltage ref2, a current flows from the output of the amplifier 131 through the capacitor C1, the resistor R3, the resistor R1, and the diode D1, charging the capacitor C1, thereby increasing the output of the amplifier 131. In this case, since the diode D2 is arranged in the direction opposed to that of the current flow, the current does not flow into the input D.
On the contrary, when the two outputs U' and D of the phase comparator 124 are both higher than the reference voltage ref2, a current flows from the input D through the diode D2, the resistor R2, the resistor R3, and the capacitor C1 to the output of the amplifier 131, discharging the capacitor C1, thereby reducing the output of the amplifier 131.
The difference between the amounts of charges with which the capacitor C1 is charged and discharged is proportional to the difference between the pulse widths of the two outputs of the phase comparator 124 when the resistor R1 and the resistor R2 are set such that they have the same resistance. When the outputs U' and D of the phase comparator 124 have the same pulse width, the output FC of the amplifier is constant. When the output U' of the phase comparator 124 has a broader pulse width than the output D, the output FC of the amplifier 131 becomes higher. When the output D of the phase comparator 124 has a broader pulse width, the output FC of the amplifier 131 becomes lower.
The output of the charge pump/loop filter 125 is input to the frequency control terminal FC of the voltage-controlled oscillator 126. One of ICs that can be used for this voltage-controlled oscillator 126 is SN74LS624 (product name) of Texas Instrument, which outputs a signal having a frequency proportional to that of the frequency control input FC within the preset frequency range.
The output of the voltage-controlled oscillator 126 is divided in frequency by a factor of 2 by the divider 127 in order to make the duty ratio 1:1. The resultant signal is the sampling clock SC. The obtained sampling clock SC is fed back to the phase comparator 124, and also used as a clock for sampling the binary reproduction signal RF2 in the flip-flop 123. The sampling clock SC is further used as a control signal for buffer memory control and other purposes.
Therefore, when the pulse width of the output U' of the phase comparator 124 is broader than that of the output D, the frequency of the sampling clock SC becomes higher, and when the pulse width of the output U' is smaller than that of the output D, the frequency of the sampling clock SC becomes lower, in the processing section shown in FIG. 6. When the two outputs U' and D of the phase comparator 124 have the same pulse width, the frequency of the sampling clock does not change.
The process in which the sampling clock SC is synchronized with the binary reproduction signal RF2 will be described below in detail.
FIG. 9A is an outlined view of optical-spot scan on pits. FIG. 9B shows the corresponding reproduction signal, and FIG. 9C shows the corresponding binary reproduction signal. FIGS. 9D, 9E, and 9F illustrate the timing of the signals at the terminals shown in FIGS. 6 and 7. FIG. 9D shows the signal timing for the case in which the phase of the binary reproduction signal RF2 match that of the sampling clock SC. FIG. 9E shows the signal timing for the case in which the phase of the sampling clock lags by 0.25T (25%) against that of the binary reproduction signal RF2. FIG. 9F illustrates the signal timing for the case in which the phase of sampling clock leads by 0.25T (25%) against that of the binary reproduction signal Rf2.
In FIG. 9A, pits 113d, 113e, and 113f are pits like the pits 113a, 113b, and 113c shown in FIG. 4, which are optical marks having a lower reflectance than the surroundings. Optical diffraction according to their mechanical shapes, dent or protrusion, may be used for these pits, in addition to the optical density. The pit 113d is a minimum pit having a length of 1T. The pit 113e is twice as wide as the minimum pit, having a length of 2T. The gap between the pits 113d and 113e is a minimum gap, having a length of 1T. The gap between the pits 113e and 113f is twice as wide as the minimum gap, having a length of 2T. This example shows a case in which pit lengths and gap lengths conform to the standard.
When the optical spot moves relative to the recording medium such that the optical spot 110 passes through the pits 113d, 113e, and 113f shown in FIG. 9A in the direction indicated by an arrow, as shown in FIG. 4, the RF signal shown in FIG. 9b is obtained due to a low optical reflectance at the pits. This obtained RF signal is input to the comparator 122 shown in FIG. 6 in order to get the inverted binary reproduction signal RF2 shown in FIG. 9C.
In the case shown in FIG. 9D, the output U of the flip-flop 128 and the output D of the AND circuit 130 have a width of 0.5T, which is half the time (1T) required for scanning the minimum pit length. The rising edge of the sampling clock SC, which is the sampling point in sampling the binary reproduction signal RF2, is located at the center of 1T in each pit or each pit gap, leaving the maximum margin for fluctuation in the scanning speed of the optical spot.
In the case illustrated in FIG. 9E, since the pulse width of the output U of the flip-flop 128 is larger than that of the output D of the AND circuit 130 by 0.25T, the frequency of the sampling clock SC increases so that the sampling clock SC catches up with the binary reproduction signal RF2.
In the case illustrated in FIG. 9F, since the pulse width of the output U of the flip-flop 128 is smaller than that of the output D of the AND circuit 130 by 0.25T, the frequency of the sampling clock SC decreases so that the sampling clock SC shifts backward to match the binary reproduction signal RF2.
In the examples shown in FIGS. 9D, 9E, and 9F, the pit length and pit-gap length conform to the standard. This means that the margin is 0.5T (50%). If the phase of the sampling clock SC shifts by 0.25T (25%) against that of the binary reproduction signal RF2 as shown in FIGS. 9E and 9F, data can be reproduced correctly as 1T, 1T, 2T, and 2T.
In reproducing a signal, when the PLL synchronizing signal starts being input, the sampling clock SC is quickly synchronized with the binary reproduction signal RF2, and RF-signal jitter caused by fluctuation in the scanning speed of the optical spot is followed, as described above. In this process, however, the time constant .tau. of the charge pump/loop filter could not be changed according to conditions, in the conventional system, causing the following problems.
The problems will be described by referring to FIG. 10, which is a graph illustrating a synchronization process in which the sampling clock SC synchronizes with the reproduction signal with different time constants. In FIG. 10, two curves are shown, curve X with a small time constant .tau. of the charge pump/loop filter, and curve Y with a large time constant .tau.. The vertical axis indicates the frequency, the horizontal axis indicates the time required for synchronization, point B indicates the point where the sampling clock SC synchronizes with the binary reproduction signal on the curve X, and point C is the point where the sampling clock SC synchronizes with the binary reproduction signal on the curve Y.
As indicated by the curve X in FIG. 10, when the frequency band in which the operation of the PLL control signal generator is ensured is set to a broad band, that is, the time constant .tau. of the charge pump/loop filter is set small, the response becomes faster, and the sampling clock SC synchronizes with the binary reproduction signal RF2 at the point B where the PLL synchronizing signal is still being input. However, if the reproduction signal is lost due to dust, scratches, or defects on the recording medium, synchronization miss easily occurs, and data cannot be correctly read.
On the other hand, as indicated by the curve Y in FIG. 10, when the frequency band in which the operation of the PLL control signal generator is ensured is set to a narrow band, that is, the time constant .tau. of the charge pump/loop filter is set large, the response becomes slower, and synchronization miss does not occur easily if the reproduction signal is lost due to dust, scratches, or defects on the recording medium during the synchronization process. However, the sampling clock SC cannot be synchronized with the binary reproduction signal RF2 while the PLL synchronizing signal 200 is being input. Therefore, if the synchronization is achieved at point C after the PLL synchronizing signal 200, for example, the data-read-start-position synchronizing signal 201 cannot be detected. In addition, RF-signal jitter caused by fluctuation in the scanning speed of the optical spot cannot be followed, disabling the data to be read correctly after all.